Integrated circuit arrangement with a number of structural elements and method for the production thereof

ABSTRACT

An integrated circuit arrangement having a number of structural elements, at least one of which is surrounded by a metallic shielding structure. This structural element is thus protected against interference due to disturbing impulses from its environment. In particular, the structural elements of the circuit arrangement can be arranged next to or on top of one another. To produce the metallic shielding structure of a structural element of the circuit arrangement, at least one depression which surrounds the structural element is created and then lined with metal. The contacts and electrical connections of the structural element are electrically insulated from the metal of the shielding structure. To connect two structural elements within a three-dimensional circuit arrangement, the surfaces of the structural elements that face one another can be covered with two different metals, the alloy thereof having a melting point T S  above the melting point T 1  of at least one of the metals, so that heating to a temperature between the two melting points results in a permanent connection.

In modern circuit designs, in order to increase packing density andshorten connection paths, power semiconductors are integrated on onechip together with their control logic. Examples of this are found inmotor controls or in ABS circuits and airbag drives in the automotivefield. It is necessary here to protect the sensitive drive logic fromthe interference of strong disturbing influences from the powersemiconductor.

Previously, the drive logic of the power semiconductors was separatedgalvanically (cf. A. Nakagawa et al., ISPS 1990, p. 97 to 101). To thisend, the modules were integrated on silicon wafers comprising a thinSiO₂ layer beneath the active Si region. The galvanic separation wasobtained by etching trenches around the circuits, said trenchesextending to the insulating SiO₂ layer.

The thus obtained shielding of the drive logic against interference isinadequate against high-frequency disturbing impulses, however. Rapidswitching processes can trigger an uncontrolled responding of the logic.

U.S. Pat. No. 5,306,942 teaches an integrated circuit arrangement withat least one structural element that is delegated in a first substrate,which element is shielded by a shielding structure from electricalfluctuations of the first substrate caused by another structural elementof the circuit arrangement. To this end, a shielding structure iscreated which surrounds a bottom half of the structural elementlaterally and comprises a bottom horizontal shielding element. Togenerate such an integrated circuit arrangement, a method is describedin which an annular depression is created in a surface of a substrate.An insulating layer and a layer of polysilicon are subsequentlydeposited. A thick layer of SiO₂ is deposited on this and planarized. Onthe planarized surface of the SiO₂ layer, a second substrate isdeposited as a carrier. The rear side of the first substrate is thenground thin, until the insulating layer is exposed. Parts of theconductive layer serve as a shielding structure. In a part of the firstsubstrate that is surrounded by the shielding structure, source/drainregions are created by implantation. A gate electrode and contacts arecreated over these. Since high temperatures are required in order todeposit the carrier and to create the source/drain regions, dopedpolysilicon, which has a high melting point, is used for the shieldingstructure.

Japanese Patent Application No. 61/290 753 demonstrates an integratedcircuit arrangement in which a lateral metallic structure is arrangednext to a structural element. To this end, depressions which are linedwith an insulating layer and filled with conductive material arearranged in a surface of a substrate at which the structural elementadjoins.

European Patent Application No. 0 567 694 describes an integratedcircuit arrangement with at least two blocks, which are separated fromone another by an insulating layer. A metallic plate is arranged betweenthem, in order to limit the capacitive coupling between the first andsecond blocks.

U.S. Pat. No. 5,122,856 describes a circuit arrangement which isintegrated in a substrate, which arrangement can switch electricalsignals from a surface of the substrate to a rear side of the substrate.To this end, depressions are made in the rear side of the substrate,which are lined with an insulating layer. A contact element extendsalong a sidewall of the depression. Stacks comprising structuralelements can be arranged on top of each other in that electrodes of thestructural elements are connected to one another by heating.

U.S. Pat. No. 5,266,511 describes a three-dimensional integrated circuitarrangement in which substrates comprising structural elements arestacked on top of one another. The structural elements are arranged inmonocrystalline layers. The connecting of the substrates is accomplishedby heating two adjacent SiO₂ layers of the substrates to approximately900° C. Structural elements that are stacked on top of one other areelectrically connected to one another other by contacts

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an integratedcircuit arrangement in which structural elements are shielded againstinterference, even high-frequency disturbing impulses, and a method forthe production thereof.

This object is inventively achieved in accordance with the invention bya metallic shielding structure that acts as a Faraday cage, whichstructure surrounds the structural element to be protected, and in amethod for the production therof.

The term “structural element” is used here for individual elements suchas diodes and transistors as well as for circuit structures comprising anumber of elements.

Protecting structural elements with a metallic shielding structurebrings the advantage of avoiding the high costs associated with the useof the above described wafers containing SiO₂.

By the metallic shielding structure, the structural elements areprotected from interfering impulses not only of neighboring powersemiconductors, but of any origin. The necessity for an additionalshielding against interfering impulses from the environment is forgone.This keeps the volume of the chip particularly small.

The structural elements can be integrated into a three-dimensionalcircuit arrangement. Substrates comprising structural elements are thusjoined on top of each other in a stacked fashion. Compared to the commontwo-dimensional arrangement, which is conditional to the use of a commonsubstrate material for all modules, the three-dimensional arrangementincreases the combinatorial possibilities with regard to the materialand production process of the various structural elements. Sensorelements or high-speed GaAs-Hf transistors can thus be combined withsilicon CMOS logic, for example.

To produce one part of the shielding structure, the surfaces of thestructural elements are provided with a metallic layer, and theirelectrical contacts are subsequently electrically insulated from themetallic layer by etching away the metallic layer around the contacts.It is advantageous to use two different metals for the metallic layersof two structural elements that are arranged adjacently in the stack,the alloy of which has a melting point above the melting point of atleast one metal. If the structural elements are now brought together,and their metallic layers are heated to a temperature below the meltingpoint of the alloy, at which one metal is solid and the other liquid,then the metals mix, which results in a hardening, due to the highermelting point of the alloy. The metals of the shielding structurethereby simultaneously serve to permanently connect two adjacentstructural elements in the stack.

It is advantageous to use tin as one metal, since it has a low meltingpoint. Copper can be chosen as the other metal.

It is advantageous to deposit an auxiliary layer made of Ti or TiN priorto applying the metals onto the surface, which layer improves theadhesion of the metallic layer and forms a barrier against diffusion ofthe metals into metallic parts of the surface of the structuralelements.

It is advantageous to apply an additional auxiliary layer of copperprior to the application of the tin, in order to improve the adhesionfurther.

These and other features of the invention(s) will become clearer withreference to the following detailed description of the presentlypreferred embodiments and accompanied drawings.

FIG. 1 is a cross-section through a first substrate, in whose top layerthere is a structural element with a top and a bottom contact, and withan electrical connection, this being surrounded by a first lateralshielding element in the top layer, which is interrupted for purposes ofleading the electrical connection through.

FIG. 2 is a cross-section through the first substrate of FIG. 1, onwhose top surface an auxiliary layer and a top horizontal shieldingelement is deposited.

FIG. 3 is a cross-section through a second substrate, in whose top layerthere is a structural element with a top and a bottom contact and withan electrical connection, this being, surrounded by a depression in thetop layer, which is interrupted for purposes of leading the electricalconnection through.

FIG. 4 is a cross-section through the second substrate of FIG. 3, onwhose top surface an auxiliary layer is deposited and a top horizontalshielding element and a first lateral shielding element are created.

FIG. 5 is a cross-section through a third substrate, in whose top layerthere is a structural element with a top and a bottom contact and withan electrical connection, this being surrounded by a depression that isprovided with an insulating layer.

FIG. 6 is a cross-section through the first substrate of FIG. 2, whichis ground thin from below and in which depressions are created on itsbottom surface, which depressions encounter the first lateral shieldingelement in the top layer, on one hand, and the bottom contact of thestructural element, on the other hand. The sidewalls of the depressionsand the bottom surface of the substrate are provided with an insulatinglayer.

FIG. 7 is a cross-section through the first substrate of FIG. 6subsequent to the deposition of an auxiliary layer and of a bottomshielding element onto the bottom surface.

FIG. 8 is a cross-section through two substrates arranged one on top ofthe other and which are connected.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Referring to FIG. 1, in a first embodiment, a first substrate 1, such asan unthinned semiconductor wafer consisting of monocrystalline siliconor of a III-V semiconductor, comprises one or more structural elements.In its top layer, a structural element of the first substrate 1 containsa transistor or a circuit structure consisting of a number of metaland/or semiconductor layers embedded in an insulating environment, whichcan contain intermetallic oxides, for example (not illustrated indetail). The region of the circuit structure is referenced S. Thestructural element comprises electrical contacts and connections. FIG. 1depicts a top contact K1, a bottom contact K2 and an electricalconnection E. If the structural element should be shielded, then a firstlateral shielding element A1 a made of metal surrounds the region of thecircuit structure S. It is interrupted at the location of the electricalconnection E so as to avoid an electrical contact from the first lateralshielding element A1 a to the electrical connection E. The first lateralshielding element A1 a is created at the same time as the circuitstructure and thus consists of the same metal as the metallic parts ofthe circuit structure.

Referring to FIG. 2, a top auxiliary layer H1 is deposited on a surfaceof the substrate 1, and on top of this a metallic top horizontalshielding element A2 a. To this end, a first layer is initially createdby sputtering. The first layer consists of a material such as Ti or TiNwhich facilitates the wetting of the surface with metal and which is 100nm thick, for example. A second layer made of metal is subsequentlydeposited over the first layer by sputtering or evaporation with anelectron beam. The second layer contains copper, tin, gallium, nickel,or tungsten, and is 1-2 μm thick, for example. By anisotropic etchingwith the aid of a mask made of photosensitive resist (not illustrated),parts of the first and second layer that do not cover the structuralelement are removed, on one hand, and the contact K1 is electricallyinsulated, on the other hand. The top auxiliary layer H1 and the tophorizontal shielding element A2 a thus emerge. Given the use of a metalof the second layer that wets the surface effectively without the topauxiliary layer H1, it is possible to forgo the top auxiliary layer H1.Given the use of tin, an additional auxiliary layer can be deposited,for instance a copper layer 20 nm thick which is formed like the topauxiliary layer H1 and which is located above the top auxiliary layerH1.

Referring to FIG. 3, in a second embodiment, a substrate 1′ comprises atleast one structural element, a top contact K1′, a bottom contact K2′,and an electrical connection E′ are provided, analogously to the firstexemplifying embodiment. A mask (not illustrated) made of photosensitiveresist is deposited on the substrate 1′. The mask made of photosensitiveresist is used as an etching mask in an anisotropic etching for purposesof creating a depression V′, for instance a plasma etching. Thedepression V′ surrounds the structural element laterally. Above theelectrical connection E′, the depression V′ comprises an interruption U.In the framework of the invention, the depression V′ may also beextended above the electrical connection E′, whereby the bottom of thedepression V′ at this point does not reach the electrical connection E′,so that insulating material completely surrounds the electricalconnection E′ (this is not illustrated).

Referring to FIG. 4, on a surface of the substrate 1′, a top auxiliarylayer H1′ is deposited, and on top of this a metallic top horizontalshielding element A2 a′ and a first lateral shielding element A1 a′. Tothis end, a first layer and a second layer are created, as in the firstembodiment. By anisotropic etching with the aid of a mask made ofphotosensitive resist (not illustrated), parts of the first and secondlayers, which do not cover the structural element, are removed, on onehand, and the contact K1′ is electrically insulated, on the other hand.The top auxiliary layer H1′, the top horizontal shielding element A2 a′,and the first lateral shielding element A1 a′, thereby emerge.

Referring to FIG. 5, in a third exemplifying embodiment, a substrate 1″comprising at least one structural element, a top contact K1″, a bottomcontact K2″, and an electrical connection E″ are provided, as in thefirst and second embodiments. A mask made of photosensitive resist isused as an etching mask in an anisotropic etching, for instance a plasmaetching, for purposes of creating a depression V″. The depression V″surrounds the structural element laterally and extends above theelectrical connection E″ up to the electrical connections E″ whichprevents a deeper etching and thus acts as an etching stop. Subsequentto the creation of the depression V″, an insulating layer is depositedon the surface and structured by anisotropic etching with the aid of amask made of photosensitive resist (not illustrated). An insulation 2 isthus created, which covers the sidewalls of the depression V″ andsurfaces of the electrical connection E″.

A procedure analogous to that in the second embodiment is then followedfor purposes of creating a top auxiliary layer H1″, a top horizontalshielding element A2 a″ and a first lateral shielding element A1 a′ (notshwon).

Referring to FIG. 6, in the context of the first embodiment of theinvention, subsequent to producing the top horizontal shielding elementA2 a on a top surface of the substrate 1, a carrier may be cemented on,whereupon a bottom side of the substrate 1 may be ground thin.Insulating material such as SiO₂ is deposited on a resultant bottomsurface of the substrate 1 by means of sputtering, so as to cover thebottom surface completely. A mask made of photosensitive resist (notillustrated) is then deposited on the bottom surface. The photosensitiveresist mask is used as an etching mask in an anisotropic etching such asa plasma etching for purposes of creating a depression V1, orrespectively, V2. The depression V1 is made so as to encounter the firstlateral shielding element A2 a from below. The depression V2 extends upto the bottom contact K2. Insulating material such as SiO₂ is depositedsurface-wide by sputtering, the bottom surface a being more denselycovered by insulating material than side surfaces and floors of thedepression V1 and of the depression V2. The insulating material at thefloors of the depression V1 and the depression V2 is then removed byanisotropic etching, producing an insulation I that covers thedepressions V1 and V2 only at the sidewalls and at the bottom surface.

Referring to FIG. 7, subsequently a bottom auxiliary layer H2 isdeposited on the bottom side of the substrate 1, and on this a metallicsecond lateral shielding element A1 b and a bottom horizontal shieldingelement A2 b. To this end, a third layer is created by sputtering. Thethird layer consists of a material such as Ti or TiN which facilitatesthe wetting of the surface with metal and is 100 nm thick, for example.A fourth metallic layer is then deposited over the third layer bysputtering or evaporation with an electron beam. The fourth layercontains copper, tin, gallium, nickel or tungsten and is 1-2 μm thick,for example. With the aid of a photosensitive resist layer (notillustrated), by means of anisotropic etching, parts of the third andfourth layers not covering the structural element are removed, on onehand, and the bottom contact K2 is electrically insulated, on the otherhand. Besides the bottom auxiliary layer H2, the bottom horizontalshielding element A2 b and the second lateral shielding element A1 bthereby emerge, which produce a shielding structure for the structuralelement in conjunction with the top horizontal shielding element A2 aand the first lateral shielding element A1 a. Given the use of a metalof the fourth layer which wets the surface of the insulation Ieffectively, the auxiliary layer H2 can be forgone. Given the use oftin, an additional auxiliary layer can be deposited which containscopper 20 nm thick, for example, and which is located over the bottomauxiliary layer H2, this being formed like the auxiliary layer H2. It isadvantageous to cover the depression V1 (FIG. 6) by an insulating 1layer only at the sidewalls, since this results in an electrical contactbetween the first lateral shielding element A1 a and the second lateralshielding element A1 b, thereby guaranteeing a uniform voltage potentialof the shielding structure. Further embodiments derive from the secondembodiment on the basis of an analogous method at substrate 1′, and fromthe third embodiment, at substrate 1″.

Referring to FIG. 8, to produce a three-dimensional circuit arrangement,in an embodiment two substrates 1 a and 1 b are arranged one on top ofthe other. Substrate 1 a comprises a top electrical contact K1 *, abottom electrical contact K2*, an electrical connection E*, a firstlateral shielding element A1 a*, a second lateral shielding element A1b*, a top horizontal shielding element A2 a*, a bottom horizonatalshielding element A2 b*, an insulation I*, a top auxiliary layer H1*,and a bottom auxiliary layer H2*, analogous to the third embodimentillustrated in FIG. 7. The substrate 1 b comprises a top electricalcontact K1**, a bottom electrical contact K2**, an electrical connectionE**, an insulation * and a bottom auxiliary layer H2**, analogously tothe third embodiment illustrated in FIG. 7. A metallic layer (notillustrated) covers the auxiliary layer H2**. The substrates arearranged such that the contact K2** is electrically connected to thecontact K1*. The metallic layer and the top horizontal shielding elementA2 a are soldered together, the substrates 1 a and 1 b being permanentlyconnected in this way.

It is advantageous to choose different metals for the metal of themetallic layer and for the metal of the top shielding element A2 a, thealloy of which has a high melting point lying above the melting point ofat least one metal. The connection of the substrates 1 a and 1 b is thenaccomplished by heating to a temperature below the melting point of thealloy, at which one metal is solid and the other is liquid, whereby themetals mix, resulting in a hardening due to the higher melting point ofthe alloy. The metal of the top horizontal shielding element A2 a* thussimultaneously serves to permanently connect the substrates 1 a and 1 b.

In an embodiment, the bottom side of the substrate 1 a may be connectedto the bottom side of the substrate 1 b, or the top side of thesubstrate 1 a may be connected to the top side of the substrate 1 b. Inthe latter case, it is advantageous to provide the top side of thesubstrate 1 b with a metallic layer which encounters the top horizontalshielding structure A2 a* in the joining of the substrates 1 a and 1 b.

In an embodiment, more than two substrates may be connected into astack.

In an embodiment, at least one unthinned substrate such as that fromFIG. 1 or FIG. 2 may be incorporated into the stack.

In the context of the invention, the connecting of different substratesmay be accomplished by other methods, such as via adhesive layersaccording to Y. Hayashi et al, Symp. on VLSU Technl (1990), page 95 to96.

Although modifications and changes may be suggested by those of ordinaryskill in the art, it is the intention of the inventors to embody withinthe patent warranted hereon all changes and modifications as reasonablyand properly come within the scope of their contribution to the art.

What is claimed is:
 1. An integrated circuit arrangement including anumber of structural elements having a number of contacts and a numberof electrical connections, said integrated circuit arrangementcomprising: a substrate made of a semiconductor material and having atop layer, said structural elements being arranged in said top layer;and a metallic shielding structure surrounding at least one of saidstructural elements, said shielding structure including a number oflateral shielding elements for shielding at least a side of saidstructural element, a top shielding element for shielding a top of saidstructural element, and a bottom shielding element for shielding abottom of said structural element, said lateral shielding elements beingarranged at least partially in said substrate and being separated fromsaid substrate by an insulation.
 2. The integrated circuit arrangementas claimed in claim 1, wherein said shielding structure completelysurrounds said structural element up to regions that surround saidcontacts and said electrical connections of said structural element. 3.The integrated circuit arrangement as claimed in claim 1, wherein atleast one of said structural elements is selected from the groupconsisting of bipolar transistors, GaAs transistors, HEMT, MESFET, HBT,thyristors, CMOS logic, bipolar logic, and ECL.
 4. The integratedcircuit arrangement as claimed in claim 1, wherein said structuralelements are arranged next to and beneath one another.
 5. The integratedcircuit arrangement as claimed in claim 4, wherein said substratefurther comprises a number of substrates including a number ofstructural elements, said number of substrates being arranged on top ofeach other in a stack; and wherein each of said structural elements issurrounded by a shielding structure and is separated from said shieldingstructure by an insulating layer, said shielding structure havinglateral shielding elements inside a respective substrate and horizontalshielding elements between adjacent substrates, said lateral shieldingelements and said horizontal shielding elements being interrupted byinsulating regions, said insulating regions including regionssurrounding said contacts and said electrical connections of saidstructural elements.
 6. The integrated circuit arrangement as claimed inclaim 5, wherein said horizontal shielding elements and parts of saidcontacts of said structural elements contained in said substrates arelocated an adjacent surfaces of said stacked substrates.
 7. Theintegrated circuit arrangement as claimed in claim 5, wherein saidinsulating regions surrounding said electrical connections betweenstructural elements of a substrate contain intermetallic oxides.
 8. Theintegrated circuit arrangement as claimed in claim 5, wherein saidinsulating regions surrounding said contacts between structural elementsof different substrates are holes.
 9. The integrated circuit arrangementas claimed in claim 6, wherein said structural elements being mutuallyinsulated by intermetallic oxides are adjacent at one surface of each ofsaid substrates; and wherein a layer of a first substrate is adjacent asurface of a second substrate, said layer being separated from saidsurface of said second substrate by an insulating layer when said layeris not insulating.
 10. The integrated circuit arrangement as claimed inclaim 5, wherein said lateral shielding elements contain an alloy of afirst metallic component and a second metallic component, said firstmetallic component being solid at a processing temperature anddissolving into said second metallic component being a liquid at saidprocessing temperature, resulting in a hardening of mixed first andsecond metallic components.
 11. The integrated circuit arrangement asclaimed in claim 5, wherein at least one horizontal shielding element ofa first substrate comprises a first metallic component, and at least onecontact of a second substrate adjacent said first substrate comprises asecond metallic component, one of said first and second metalliccomponents being a solid and dissolving into another of said first andsecond metallic components being a liquid at a processing temperatureand thereby hardening for forming a permanent connection between saidfirst substrate and said second substrate.
 12. A method for theproduction of an integrated circuit arrangement including a number ofstructural elements having a number of first contact, a number of secondcontacts and a number of electrical connections, the method comprisingthe steps of: creating a number of structural elements in a top layer ofa substrate made of semiconductor material; forming an insulation onsaid substrate; and surrounding at least one of said structural elementswith a metallic shielding structure by creating a number of top andbottom lateral shielding elements, a top horizontal shielding element,and a bottom horizontal shielding element, said lateral shieldingelements being created at least partially in said substrate and beingseparated from said substrate by said insulation.
 13. The method asclaimed in claim 12, wherein said shielding structure completelysurrounds said structural element, up to regions surrounding said firstcontacts, said second contacts and said electrical connections.
 14. Themethod as claimed in claim 12, further comprising the steps of: coatinga top surface of said substrate with a metallic layer; wherein said tophorizontal shielding element is created from said metallic layer byetching around contact surfaces of said first contacts to insulate saidfirst contacts from said metallic layer; cementing said top surface ofsaid substrate onto a carrier; grinding thin said substrate from abottom surface of said substrate; creating first depressions and seconddepressions on said bottom surface of said substrate, said seconddepressions extending to said second contacts included in saidsubstrate; providing an insulation on said bottom surface of saidsubstrate and on sidewalls of said first depressions and said seconddepressions; coating said first depressions, said second depressions andsaid bottom surface of said substrate with metal, said metal coating ofsaid second depressions providing a conductor from said second contactsto said bottom surface of said substrate, said metal coating of saidfirst depressions creating metallic layers that completely surround saidstructural elements laterally, up to interruptions and thereby creatinga bottom lateral shielding element; forming interruptions of saidmetallic layers of said top and bottom lateral shielding elements atleast in regions of said electrical connections for preventing anelectrical contact between said metallic layers and said electricalconnections; and etching away said metal on said bottom surface of saidsubstrate around contacts surfaces of said second contacts to a such adepth that insulating regions of said substrate are obtained.
 15. Themethod as claimed in claim 14, further comprising the step of: prior tocoating said top surface of said substrate with a metallic layer,creating a number of first and second top depressions in said topsurface of said substrate.
 16. The method as claimed in claim 15,wherein said first top depression is created to laterally surround astructural element, said first top depression is interrupted over anelectrical connections of said structural element, said first topdepression does not reach conductive regions of said substrate; andwherein said first depression is created to contact said first topdepression.
 17. The method as claimed in claim 15, wherein said secondtop depression laterally surrounds a structural element, said second topdepression extends to an electrical connection of said structuralelement from above said electrical connection, said second topdepression has an insulating layer; and wherein said first depression iscreated to contact said second top depression.
 18. The method as claimedin claim 15, further comprising the step of: prior to coating said firstand second depressions and said second top depression with metal, andprior to coating said top and bottom surfaces of said substrate withmetal, applying an additional layer at said locations at which saidmetal is subsequently deposited, said additional layer improvingadhesion of said metal and preventing diffusion of said metal into saidfirst and second contacts.
 19. The method as claimed in claim 14,further comprising the step of: permanently connecting a number of saidsubstrates into a stack, said second depression and said first contactsof said substrates being arranged such that second depressions and firstcontacts of one substrate encounter allocated second depressions andfirst contacts of an adjacent substrate.
 20. The method as claimed inclaim 19, wherein metals coated on surfaces of adjacent stackedsubstrates are different, and an alloy of said different metals onsurfaces of two adjacent substrates comprises a melting point above amelting point of at least one of said metals; and wherein said adjacentsubstrates as connected by heating to a temperature below a meltingpoint of said alloy, at which temperature one metal is solid and theother is liquid, said metals thereby mixing, resulting in a hardeningdue to said higher melting point of said alloy.